Arash Daghighi

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Research

 

 

  • I Conduct Independent Research and Have a Wide Profile.

 

  •      2015-2016, Developed a technique to reduce the inherent thermal cross-talk in integrated circuits incorporating Silicon-on-Diamond substrate. It is well-known that Silicon-on-Diamond substrate can sustain more than 10 times power-density than that of Silicon-on-Insulator. However, there is no comment regarding the thickness of buried diamond layer. A thermal-mismatch-aware design of high power-density integrated circuits dictates that the buried diamond layer requires to be sufficiently thinned. 
       
  •      2014-2015, Extended the Idea of Diamond-Shaped Body-Contact to SOI LDMOSFETs to improve the on-state breakdown voltage and to enhance the reliability of the devices. The DSBC structure is a strong candidate for SOI LDMOSFET applications where devices with smaller area at a given Ron is a key design parameter.  
       
  •     2011-2012, Developed Transition-Free concept for improving linearity of Silicon-on-Insulator radio-frequency circuits.  A novel method demonstrates the transition-free circuit design procedure.  The method is used to design a 2.4 GHz PD SOI LNA.  Mixed-mode device-circuit simulations showed improved THD and OIP3. The transition-free concept is filed with USPTO.
  •     2009-2010, Developed a structure demonstrating a Novel Nano-Scale Ultra-Thin-Body Silicon-on-Insulator MOSFET.  Drain-induced-barrier-lowering of the double-insulating Silicon-on-Diamond transistor is considerably improved while retaining the same Power-Density.  Fabrication process steps were explained.  The invented structure is filed with USPTO.  
  •     2004-2005, Designed and simulated Digital ECC (Error – Correction - Code) emulator circuitry for SRAM Vccmin evaluation, which was used in Intel next generation 45nm technology. Designed and implemented Catch-ram Digital circuitry to extract on-chip SRAM fail-map which was used in Intel’s X6 lead vehicle. This enhanced technology learning, identified technology and design directions. Designed and simulated RF (Register File) bit-cell for minimum standby Vccmin and very small fail rate for the 65nm and 45nm technologies. Simulated and verified critical paths in the Digital I-O block of SRAM to ensure min-delay specifications based on the final layout and design. This confirmed smooth transition from previous generation to the next generation.
  •     2003-2004, Developed an Area-Efficient Body-Contact-Structure for partially-depleted Silicon-on-Insulator, SOI, low and high-voltage MOSFET and analyzed by three-dimensional device simulation.  DC device analysis and AC parameters extraction by ISE TCAD Process and Device simulation tool base on non-isothermal drift-diffusion model was developed.  Improved performance was achieved incorporating the novel Body-Contact structure.  The design and development of Diamond-Shaped Body-Contact SOI Devices were described and sub-circuit was prepared in 0.35 um MOI5 Process targeted for RF application.  DSBC structures were designed by the standard-layers of the process.  Device characterization was performed.  Experimental measurement confirmed the Area-Efficiency of the DSBC SOI MOSFETs, FB suppression and excellent current drive performance. 
  •     2001-2003, Device characterization and electronic circuit design for low-temperature operation using 0.35um SOI CMOS. Design and implementation of high-speed analog signal transmission for image sensor operated at low temperature. Design, simulation and layout of high-speed, wide bandwidth current feedback CMOS operational amplifier. Design and implementation of LC balanced Voltage Controlled Oscillators (VCO). 2.4GHz and 5GHz SOI VCO Design, simulation and layout using Cadence design tools. Measurement of VCO parameters including phase noise. NSF National Industry-University Co-operative Research Center, CDADIC, Develop high-speed analog signal transmission for low temperature operation of image sensor.  Design and implemented LC-balanced voltage controlled oscillators.  2.4 GHz SOI VCO design and layout by Cadence design tool. 
  •     1997-2001, Managed department of 10 electrical technicians for maintenance of electronic systems, ABB PLCs, AC and DC machines and drives up to 300kW. Full responsibility for the maintenance, repair and development of electrical and electronic equipment of polymer fiber production machinery. Designed and implemented the electrical and electronic part of a non-woven carpet designer machine to wind and unwind carpet roles, reducing total cost of $50,000. Developed Memory Modules for DC drives resulting in $1000/each company savings. Designed and implemented computer interface board and drive circuits for rotation of stepper motor as position controller. Developed a C program to simulate function of the mechanical machine. Designed, laid out and tested a 12-bit Analog to Digital PCB board for a PC based PLC system used in an industrial automation system: 16 differential analog input channels (32 single ended), Software programmable sampling time, Full electrical isolation of the Analog part from the Digital circuitry incorporating optocoupler.
  •     1995-1997, Part time cooperation in qualification of research projects and articles. Participated in the “Best research project” and took the 5th rank. Published a paper on the research difficulties and requirement in the “Payam-e-matn” magazine dated June 1997.
  •     1997, M.Sc. Thesis, Design and Fabrication of a 2-input 2-output Benchmark Laboratory-System and Design of a Flexible-Neural-Network as a Process Controller. The neural-network control algorithms were written using C program. The research-outputs were published in Conferences.
  •     1995, B.Sc. Thesis, Design and Fabrication of a Microprocessor-oriented Digital Display. The Dot-matrix of LEDs were properly designed, powered-on, programmed and controlled by Z-80. The Zelog micro-processor and its peripherals were fabricated.


 

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